1. Field of the Invention
The present invention relates to a semiconductor signal processing device, and particularly to a configuration of a semiconductor signal processing device including an operational circuit in which a semiconductor memory is used.
2. Description of the Background Art
A system LSI (Large Scale Integration) called SoC (System on Chip) is widely used to achieve down-sizing, weight-lighting and speed-up of a processing system. In SoC, a memory and a logic (processing device) are integrated on a common semiconductor substrate. In the system LSI, because the memory and the logic are connected by on-chip interconnections, a large amount of data can be transferred at high speed to allow the high-speed processing. In an article by K. Arimoto et, al., titled “A Configurable Enhanced T2RAM Macro for System-Level Power Management Unified Memory,” 2006 Symposium on VLSI Circuits, Digest of Technical Papers, June 2006 (hereinafter referred to as Non-Patent Document 1), TTRAM (Twin Transistor Random Access Memory) is proposed as a semiconductor memory suitable for embedding in the system LSI.
In Non-Patent Document 1, a transistor having an SOI (Silicon On Insulator) structure is utilized to store data in a nonvolatile manner. A threshold voltage of a data storage transistor is changed by accumulating charges in a body region of the data storage SOI transistor, and the storage data is converted into threshold voltage information. In data reading, an access transistor is set in an on-state, and the data storage transistor is connected between a source line and a bit line. Because an amount of current flowing through the bit line depends on the threshold voltage of the data storage transistor, the data is read by sensing the bit line current.
In the configuration of Non-Patent Document 1, the charges are accumulated in the body region of the transistor having the SOI structure, so that the data can be stored in the nonvolatile manner. Because the charges are retained in the body region, data can be read in a nondestructive manner, a restoring operation in which the storage data is re-written is not required unlike DRAM (Dynamic Random Access Memory), and a read cycle time can be shortened. Data is read by sensing the current, so that the data can be read at high speed even under a low power supply voltage condition.
A memory cell is formed of two transistors, so that an occupied area by the memory cell can be reduced so that the memory cells re arranged in high density. The charges are accumulated in the body region of the transistor of the SOI structure, so that the data can stably be retained even under the low power supply voltage condition.
A need for high-speed digital signal processing for processing large amount of data such as audio and image at high speed is increased in a mobile application such as a mobile terminal equipment. In conventional software-based processing with CPU (Central Processing Unit) and DSP (Digital Signal Processor), a performance required in current multi-media processing cannot be achieved. Therefore, usually the processing with hardware logic is performed.
However, as miniaturization of the semiconductor manufacturing process and complexity of system advance, such problems are caused as cost increase of semiconductor process, and prolonged design and verification periods and resultant cost increase. Therefore, there is a strong demand to perform various kinds of large-scale data processing at high speed through replacement by software. Naturally, from the viewpoint of built-in application, there is a strong demand for high processing capability with low power consumption, that is, high-energy processing capability.
As a configuration for satisfying such demand, Japanese Patent Laying-Open No. 2006-099232, for example, discloses the one, in which an operational processing unit is disposed corresponding to each memory cell column of a semiconductor memory array and operational processing is concurrently performed in plural operational processing units. In the configuration disclosed in Japanese Patent Laying-Open No. 2006-099232, operation processing contents can be set by changing micro program contents. In the configuration disclosed in Japanese Patent Laying-Open No. 2006-099232, a sense amplifier and a write driver are disposed for each memory cell column as a data transfer circuit at a data transfer section between the memory array and the operational processing units. The memory cell is used to store operation target data and operation result data.
In the configuration disclosed in Japanese Patent Laying-Open No. 2006-099232, the SIMD (Single Instruction Multiple Data Stream) operational processing unit and the memory are closely coupled to solve a data transfer bottle neck between a memory and a processor, and operation performance close to hardware is achieved by massive parallel operation.
The configuration disclosed in Japanese Patent Laying-Open No. 2006-099232 is characterized in that fine granularity processing element of one bit or two bits is utilized and the operational processing unit performs the operation based on bit-by-bit data from the memory. That is, in the configuration disclosed in Japanese Patent Laying-Open No. 2006-099232, a plurality of operational processing units concurrently perform the operation in a bit serial fashion, thereby achieving the high-performance operation processing.
Japanese Patent Laying-Open No. 2004-264896 discloses a configuration, in which a memory cell is provided with an operation function without the use of an operational processing unit. In the configuration disclosed in Japanese Patent Laying-Open No. 2004-264896, a storage capacitor storing data and a load capacitor are connected in series between a bit line pair. A reference voltage and operation data are applied at both ends of the series-connected ferroelectric capacitors, and operation result is supplied from a connection node of the ferroelectric capacitors. In Japanese Patent Laying-Open No. 2004-264896, using a hysteresis in polarization of the ferroelectric capacitor, dependency of a moving amount of charges on match/mismatch of logical values of the storage data and operation data is utilized.
Japanese Patent Laying-Open No. 2007-213747 discloses a configuration, in which an operation of the storage data and write data is performed using one ferroelectric capacitor. In the configuration disclosed in Japanese Patent Laying-Open No. 2007-213747, a one-shot pulse signal is applied to a bit line of a bit line pair according to a logical value of the operation data, and a potential at the other of the bit line pair is amplified by a sense amplifier. In Japanese Patent Laying-Open No. 2007-213747, the dependency of the moving amount of charges of the ferroelectric capacitor on match/mismatch of logical values of the storage data and operation data is also utilized.
Japanese Patent Laying-Open No. 07-249290 discloses a configuration, in which an SRAM (Static Random Access Memory) cell is provided with an operation function. In the configuration disclosed in Japanese Patent Laying-Open No. 07-249290, access transistors of the SRAM cell have on-off control made independently of each other, and a high-side cell power supply voltage and a low-side cell power supply voltage are also controlled in a unit of a memory cell row. The bit line connection, the on-off control of the access transistors, and the control of the high-side and low-side cell power supply voltages are combined to perform various logic operations.
Japanese Patent Laying-Open No. 08-031168 discloses a configuration, in which a sense amplifier performs an operation processing of the storage data of a memory cell with the use of a DRAM (Dynamic Random Access Memory) cell. In the configuration disclosed in Japanese Patent Laying-Open No. 08-031168, plural memory cells and plural dummy cells are connected to bit lines of the bit line pair, respectively. A logic operation is performed on storage data of the plural memory cells by setting the respective storage data of the plural dummy cells at one of an intermediate value, “1” and “0”.
Japanese Patent Laying-Open No. 07-182874 discloses a configuration, in which an operation is performed with the memory cell. In the configuration disclosed in Japanese Patent Laying-Open No. 07-182874, an operational circuit is connected to a bit line and a static storage circuit, and includes an operation result output terminal. The operational circuit performs a one-bit arithmetic or logic operation on the input data received from the bit line and the data stored in the storage circuit, and supplies the operation result through the operation result output terminal.
Japanese Patent Laying-Open No. 2000-284943 discloses a configuration, in which an operation is performed using a memory cell. In the configuration disclosed in Japanese Patent Laying-Open No. 2000-284943, a semiconductor memory includes plural memory cells, a word line corresponding to an X-address, and a pair of bit lines corresponding to a Y-address. A logic operational circuit is provided for each pair of bit lines, and the plural logic operational circuits are simultaneously activated in response to a logic selection signal. The operation result of the logic operational circuit is simultaneously written in all the Y-addresses on at least one selected X-address. The logic operational circuit is provided for each pair of bit lines, so that data on all the pairs of bit lines can simultaneously be operated and thus the operation can be performed in a short time for a large amount of data.
FPGA (Field Programmable Gate Array) with an LUT (Look Up Table) mounted thereon is a logic device that can implement various logic circuits by programming a logic specification. For example, a memory having a storage capacity of N bits by M bits can implement an LUT operational unit having a function of a logic function, which outputs M-bit data for N-bit input data. A programmable LUT operational processing unit can be implemented with the use of FPGA as the memory. However, in the conventional LUT operational processing unit, the implementable logic function is directly restricted by the memory capacity.
Japanese Patent Laying-Open No. 2007-226944 discloses an LUT (Look Up Table) operational processing unit that realizes plural functions. In the configuration disclosed in Japanese Patent Laying-Open No. 2007-226944, when a control signal line connected to a memory cell is activated, the memory cell performs one of the data read and write and the output of a predetermined value constituting an operation result of the operation target data in response to a mode control signal. An address decoder receives a data write address, a data read address, or operation target data, and activates the control signal line corresponding to the received address/data based on which the mode control signal designates, the data write, the data read, or the operation processing. Therefore, a circuit scale is maintained without preparing the memory cells for storing data of a truth table, and the LUT operational processing unit having two independent operation functions is implemented.
In T. Tsuji, et al., “A 1.2V 1 Mbit Embedded MRAM Core with Folded Bit-Line Array Architecture,” 2004 Symposium on VLSI Circuits Digest of Technical Papers, June 2004, pp. 450-453 (hereinafter referred to as Non-Patent Document 2), a configuration in which MRAM is utilized is described as an example of a nonvolatile memory suitable for the built-in application. In Non-Patent Document 2, a magnetic field is induced by a current flowing through a bit line and a write word line, a magnetization direction of a free layer of an MTJ (Magnetic Tunnel Junction) element is set by the magnetic field, and a resistance value is changed due to a magneto-resistance effect. The resistance value of the MTJ element is correlated with the storage data.
In the configurations disclosed in the above-described Japanese Patent Laying-Open Nos. 2004-264896, 2007-213747, 07-249290, 08-031168, 07-182874, and 2000-284943, the logic operation is performed with the memory cell or the sense amplifier. Accordingly, there is no need to read the data stored in the memory cell outside the memory for performing the operation processing with a separately provided operational processing unit, achieving speed-up of a operation processing.
In the configurations disclosed in Japanese Patent Laying-Open Nos. 2004-264896, 2007-213747, 07-249290, and 08-031168, the operation is performed in each memory cell column, so that the operation of a fine granularity can be realized without largely adding hardware.
However, in the configuration where two series-connected ferroelectric capacitors are used as the configuration of Japanese Patent Laying-Open No. 2004-264896, although it is described that the nondestructive data read can be performed, the restoring operation is performed by writing the reverse data of the operation data after the operational processing, in order to avoid a distortion of a hysteresis characteristic of the ferroelectric capacitor during the operational processing. Accordingly, the operation data transfer, the operation, and the restoring are required during the operation. The operation cycle cannot be shortened due to the restoring, and the high-speed processing is hardly realized.
In the configuration disclosed in Japanese Patent Laying-Open No. 2007-213747, although one ferroelectric capacitor and two transfer gates are used as one operator cell, the data stored in the ferroelectric capacitor is destructively read during the operation. Accordingly, the operational processing cannot be performed by combining different operation data with the same data.
Where the ferroelectric capacitor is used as in Japanese Patent Laying-Open Nos. 2004-264896 and 2007-213747, the charge movement is utilized depending on a polarization state of the ferroelectric capacitor. Accordingly, in order to sense the moving amount of charges with the sense amplifier, it is necessary to move some charge amount. Therefore, in order to move the sufficient amount of charges, the capacitor needs to have a significant size, which becomes an obstacle against a high integration.
In Japanese Patent Laying-Open Nos. 07-249290 and 07-182874, because of the use of the SRAM cell, the number of transistor elements is increased and the cell size becomes larger than those of the MRAM cell and DRAM cell. Therefore, the large-capacity memory array is hardly realized in the small occupation area, and the configuration of Japanese Patent Laying-Open Nos. 07-249290 and 07-182874 is difficult to apply to the application in which a large amount of data are processed in a mobile equipment.
In the configuration disclosed in Japanese Patent Laying-Open No. 08-031168, the DRAM cell is used, and therefore, the cell size can be reduced. However, the data is destructively read in the DRAM cell. Particularly the storage data is completely destroyed in cases where plural memory cells are connected in parallel to one bit line as in Japanese Patent Laying-Open No. 08-031168. Accordingly, similarly to the configuration of Japanese Patent Laying-Open No. 2007-213747, the operation cannot be performed by repeatedly utilizing the data stored in the memory cell.
In the configuration disclosed in Japanese Patent Laying-Open No. 2000-284943, when the logic operational circuit is provided for each pair of bit lines, it is difficult to implement a large-capacity memory array in a small occupation area.
In the method for achieving the multifunctional memory cell as in the configuration disclosed in Japanese Patent Laying-Open No. 2007-226944, the occupation area of the memory array is significantly enlarged with the increase in storage capacity.
Where the ferroelectric capacitor and the DRAM cell are used, because a voltage sensing type sense amplifier is used as the sense amplifier that senses and amplifies the data, the sensing operation cannot be performed until a difference in voltage is sufficiently developed between the sense nodes of the sense amplifier. Accordingly, in the voltage sensing type sense amplifier, because the sensing operation is slower than that of a current sensing type sense amplifier, the operation result cannot be produced at high speed, and it is difficult to implement a high-speed operation processing.
The mobile equipment is required to operate under a low power supply voltage condition. Accordingly, where an operational processing is performed by moving the charges through the use of the capacitor, the sufficient amount of charges cannot be moved at a low power supply voltage, which results in a problem that the correct operational processing cannot be ensured.
Non-Patent Document 1 describes that a DFV (Dynamic Frequency and Voltage) control system is applied in system power supply management. However, in Non-Patent Document 1, there is no description on the configuration in which the operation is performed using a memory cell.
In Japanese Patent Laying-Open Nos. 2006-099232, 2004-264896, 2007-213747, 07-249290, and 08-031168 and Non-Patent Document 1, the operation is digitally performed. For example, when addition is digitally performed, the operation of the upper-order bit cannot be performed until a lower-order carry is ascertained. Therefore, the digital arithmetic operation cannot be performed at high speed. In Japanese Patent Laying-Open Nos. 2006-099232, 2004-264896, 2007-213747, 07-249290, and 08-031168 and Non-Patent Document 1, there is no description on a circuit-wise measure for performing the arithmetic operation such as addition and subtraction at high speed.
In Japanese Patent Laying-Open Nos. 2006-099232, 2004-264896, 2007-213747, 07-249290, and 08-031168 and Non-Patent Document 1, an address space of the storage device is uniquely determined, and there is no consideration on the configuration for expanding the address space.
Non-Patent Document 2 merely describes the configuration of the MRAM cell and the configuration of the data read, and fails to describe an internal operational processing of storage data.